As the sampling mixer in the prior art, there is the mixer that samples the current-converted signal and produces a filter effect by a switched capacitor circuit, as set forth in Patent Literature 1. FIG. 8 is a circuit diagram of the sampling mixer set forth in Patent Literature 1 in the prior art.
In FIG. 8, a sampling mixer 800 includes a transconductance amplifier (TA) 1 for converting a received radio frequency (RF) signal into a current, an in-phase sampling mixer portion 2 for sampling the RF current signal output from the TA, an opposite-phase sampling mixer portion 3, and a digital control unit 4 for generating signals to control the in-phase sampling mixer portion 2 and the opposite-phase sampling mixer portion 3.
The in-phase sampling mixer portion 2 has a sampling switch 5 composed of FET, a history capacitor (Ch) 6 for integrating the signal sampled by the sampling switch 5 over a continuous time without a discharge, rotation capacitors (Cr) 7, 8, 9, 10, 11, 12, 13, 14 for repeating an integration and a discharge of the signal sampled by the sampling switch 5, a buffer capacitor (Cb) 15 for buffering the signals discharged from the rotation capacitors 7 to 14, a damping switch 16 for connecting/disconnecting the rotation capacitors 7 to 14 and the buffer capacitor 15, a reset switch 17 for resetting the rotation capacitors 7 to 14 after the signal is discharged, integrating switches 18, 19, 20, 21, 22, 23, 24, 25 for connecting/disconnecting the history capacitor 6 and the rotation capacitors 7 to 14, and discharging switches 26, 27, 28, 29, 30, 31, 32, 33 for connecting/disconnecting the rotation capacitors 7 to 14 and the buffer capacitor 15.
The damping switch 16, the reset switch 17, the integrating switches 18 to 25, and the discharging switches 26 to 33 are composed of the (n-type) FET respectively. The n-type FET is turned ON in its high state where a gate voltage is high, and is turned OFF in its low state where a gate voltage is low. The opposite-phase sampling mixer portion 3 has the same configuration as the in-phase sampling mixer portion 2.
The digital control unit 4 has a shift register 34 using eight registers, a local oscillator (not shown), and a frequency divider (not shown) for dividing a frequency of an output of the local oscillator. The frequency divider is connected to a terminal 35 connected to the discharging switches 26 to 29, and a terminal 36 connected to the discharging switches 30 to 33.
FIG. 9 is a timing chart of control signals that the digital control unit 4 generates. A CKV_LO signal is input into a gate of the sampling switch 5. CNT_SV0 to 7 signals are input into gates of the integrating switches 18 to 25 respectively. A CNT_SAZ signal is input into gates of the discharging switches 26, 27, 28, 29 from the terminal 35. A CNT_SBZ signal is input into gates of the discharging switches 30, 31, 32, 33 from the terminal 36. A CNT_D signal is input into a gate of the damping switch 16. A CNT_R signal is input into a gate of the reset switch 17.
An operation of the sampling mixer 800 will be explained by using the in-phase sampling mixer portion 2. The TA1 converts an RF signal into an RF current signal and outputs the current signal to the in-phase sampling mixer portion 2. In the in-phase sampling mixer portion 2, the sampling switch 5 samples the RF current signal by a local oscillation (LO) signal at the substantially same frequency as the RF current signal. The sampled RF current signal is given as a discrete signal that is discretized in terms of time.
When the discrete signal is integrated by the history capacitor 6 and the rotation capacitors 7 to 14, this signal is subjected to the filtering and the decimation. At first, the rotation capacitor 7 is connected to the history capacitor 6 by the CNT_SV0 signal, and the discrete signal is integrated in a period when the CNT_SV0 signal is high (during eight periods of the CKV_LO signal).
When the CNT_SV0 signal goes to low, the rotation capacitor 7 is disconnected from the history capacitor 6. The rotation capacitor 8 is connected to the history capacitor 6 by the CNT_SV1 signal. The rotation capacitor 8 integrates the discrete signal over eight periods of the CKV_LO signal, and then is disconnected from the history capacitor 6.
Similarly, the rotation capacitors 9 to 14 are connected in order to the history capacitor 6 by the CNT_SV2 to 7 signals every eight periods of the CKV_LO signal, and integrate the discrete signal respectively. The CNT_SV0 to 7 signals are output from the shift register 34.
A signal (LO/8 signal) whose frequency is 1/8 of the LO signal is input from the frequency divider to the terminal 37 as a clock signal of the shift register. Therefore, the shift register 34 shifts the signal to the next register every eight periods of the CKV_LO signal, and generates the CNT_SV0 to 7 signals sequentially.
At this time, the shift register 34 brings about an FIR (Finite Impulse Response) filter effect by integrating the discrete signal over eight periods of the CKV_LO signal. Thus, a sampling rate is decimated to 1/8 due to such an effect that a moving average of the discrete signals is calculated over eight periods of the CKV_LO signal. This filter effect is called a first-stage FIR filter.
Also, because the rotation capacitors 7 to 14 are connected sequentially to the history capacitor 6, the in-phase sampling mixer portion 2 brings about an IIR (Infinite Impulse Response) filter effect. This filter effect is called a first-stage IIR filter.
Then, the signals integrated by the rotation capacitors 7 to 14 are discharged to the buffer capacitor 15 in response to the CNT_SAZ signal. In this case, the signals integrated by the rotation capacitors 7 to 14 respectively are discharged to the buffer capacitor 15 at a time. The damping switch 16 is turned OFF by the CNT_D signal after the signals are discharged to the buffer capacitor 15. The reset switch 17 is turned ON by the CNT_R signal to reset the signals remaining in the rotation capacitors 7 to 10 during a period the damping switch 16 is turned OFF.
At this time, the in-phase sampling mixer portion 2 has the four-tap FIR filter effect because the signals integrated by the rotation capacitors 7 to 10 respectively are discharged to the buffer capacitor 15 at a time. Thus, a sampling rate is decimated to 1/4 due to such an effect that a moving average is applied to the signals integrated by the rotation capacitors 7 to 10 respectively.
Similarly, the rotation capacitors 11 to 14 discharge the signals integrated by these capacitors respectively to the buffer capacitor 15 at a time in response to the CNT_SBZ signal. Thus, a sampling rate is decimated to 1/4 due to a four-tap FIR filter effect. This filter effect is called a second-stage FIR filter. The CNT_SAZ signal and the CNT_SBZ signal are a signal (LO/64 signal) whose frequency is given by dividing a frequency of the LO signal by 64 in the digital control unit 4 respectively.
Also, because the groups of the rotation capacitors 7 to 10 and the rotation capacitors 11 to 14 are connected sequentially to the buffer capacitor 15, the in-phase sampling mixer portion 2 brings about another IIR filter effect. This filter effect is called a second-stage IIR filter.
The opposite-phase sampling mixer portion 3 carried out the similar operation. A difference from the in-phase sampling mixer portion 2 resides in that phases of the signals being input into the gates of the sampling switch 5 and a sampling switch 38 are different by 180 degree and a timing of the sampling is shifted by 180 degree in phase. A LOB signal whose phase is shifted from the LO signal by 180 degree is input into the sampling switch 38.
The frequency characteristic of the sampling mixer 800 when a frequency of the LO signal is set to 2.4 GHz is shown in FIG. 10. According to this, it was concluded that the sampling mixer 800 has the filter effect having a gain of 23 dB and a cut-off frequency of 1.0 MHz.
Patent Literature 1: U.S. Patent Application Publication No. 2003/0083033 Specification (pp. 7-8, FIG. 11a)